A vertical type MOSFET having a trench gate structure is disclosed in, for example, JP-A-S59-8374 and JP-A-H07-326755 (corresponding to U.S. Pat. No. 5,915,180A). It is important to ensure reliability of a gate insulation film in case of manufacturing a vertical type MOSFET having a trench gate structure with SiC semiconductors. A breakdown field strength of SiC is 10 times larger than that of silicon, and therefore a working voltage applied to a SiC semiconductor device can be 10 times larger than that applied to a silicon device. In this case, a field strength produced and applied to a gate insulation film, which is formed in the trench that is disposed in SiC, is 10 times larger than a field strength produced and applied to a silicon device, and the strong filed strength easily results in a breakdown of the gate insulation film, which is located at a corner of the trench.
To ensure the reliability of the gate insulation film, JP-A-2010-21175 (corresponding to U.S. 2010/0006861 A1) teaches a method of relaxing the field concentration by rounding off corner sections of a trench. Specifically, the rounding off is performed by hydrogen etching after the trench is formed.
However, a heavily-doped N+-type layer of a trench shoulder (i.e., an entrance corner of the trench), which is removed by hydrogen etching, moves to a trench bottom as described in JP-A-2010-21175 (corresponding to U.S. 2010/0006861 A1). A prior art of forming the trench will be described with reference to FIG. 4A to FIG. 4D.
The conventional manufacturing method of the vertical type MOSFET includes following processes prior to the forming of the trench. Firstly, a N+-type drift layer J2 and a P-type base layer J3 are grown epitaxially on a surface of a N+-type SiC substrate J1 as shown in FIG. 4A. Then a N+-type source region J4 is formed on a surface of the P-type base layer J3 by implanting ions of N-type impurity at a high concentration and activating the implanted ions as shown in FIG. 4B.
A trench J5 is formed by, for example, a RIE (i.e., Reactive Ion Etching) method after an etching mask (not shown) is disposed on a surface of the N+-type source region J4 as shown in FIG. 4C. A part of the N+-type source region J4, which is placed on the trench shoulder and removed by hydrogen etching, moves to the bottom of the trench J5, and forms a N+-type high-concentration layer 36 on bottom corners as shown in FIG. 4D.
When a vertical type MOSFET having a N+-type high-concentration layer 36 operates, electric field concentrates on the gate insulation film, and the concentrated electric field results in a breakdown of the gate insulation film. Further, the N+-type high-concentration layer J6, which is formed on an inner wall of the trench J5, causes an increase in leak current between a source and a drain
Thus, it is required for a manufacturing method of a SiC semiconductor device to prevent a high-concentration layer from being generated on the bottom of the trench when a process for forming the trench gate structure such as rounding off the trench 6 is carried out.